66 inbound atu limit register 3 - ialr3, Table 93. inbound atu limit register 3 - ialr3, 66inbound atu limit register 3 - ialr3 – Intel CONTROLLERS 413808 User Manual
Page 206: 93 inbound atu limit register 3 - ialr3, Intel, Bit default description
Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
206
Order Number: 317805-001US
2.14.66 Inbound ATU Limit Register 3 - IALR3
Inbound address translation for memory window 3 occurs for data transfers occurring
from the PCI bus (originated from the PCI bus) to the 4138xx internal bus. The address
translation block converts PCI addresses to internal bus addresses.
The inbound translation base address for inbound window 3 is specified in
. When determining block size requirements — as described in
— the translation limit register provides the block size requirements for
the base address register. The remaining registers used for performing address
translation are discussed in
.
The 4138xx value register’s programmed value must be naturally aligned with the base
address register’s programmed value. The limit register is used as a mask; thus, the
lower address bits programmed into the 4138xx value register are invalid. Refer to the
PCI Local Bus Specification, Revision 2.3 for additional information on programming
base address registers.
Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12,
with a one to one correspondence. A value of 0 in a bit within the IALR3 makes the
corresponding bit within the IABAR3 a read only bit which always returns 0. A value of
1 in a bit within the IALR3 makes the corresponding bit within the IABAR3 read/write
from PCI. Note that a consequence of this programming scheme is that unless a valid
value exists within the IALR3, all writes to the IABAR3 has no effect since a value of all
zeros within the IALR3 makes the IABAR3 a read only register.
.
Table 93. Inbound ATU Limit Register 3 - IALR3
Bit
Default
Description
31:12
00000H
Inbound Translation Limit 3 - This value determines the memory block size required for the ATUs
memory window 3.
11:00
000H
Reserved
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+208H