25 atu interrupt pin register - atuipr, Table 165. atu interrupt pin register - atuipr, 26 atu minimum grant register - atumgnt – Intel CONTROLLERS 413808 User Manual
Page 316: Table 166. atu minimum grant register - atumgnt, 25atu interrupt pin register - atuipr, 26atu minimum grant register - atumgnt, 165 atu interrupt pin register - atuipr, 166 atu minimum grant register - atumgnt, This register does not apply to pci express, Intel
Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
316
Order Number: 317805-001US
3.17.25 ATU Interrupt Pin Register - ATUIPR
ATU Interrupt Pin Register bit definitions adhere to PCI Local Bus Specification,
Revision 2.3. This register identifies the interrupt pin the ATU and Messaging Unit
interface uses.
3.17.26 ATU Minimum Grant Register - ATUMGNT
This register does not apply to PCI Express.
Table 165. ATU Interrupt Pin Register - ATUIPR
Bit
Default
Description
07:00
01H
Interrupt Used - A value of 01H signifies that the ATU interface unit uses the INTA legacy interrupt
message.
PCI
IOP
Attributes
Attributes
7
4
0
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+03DH
Table 166. ATU Minimum Grant Register - ATUMGNT
Bit
Default
Description
07:00
00H
This register does not apply to PCI Express.
Hard-wired to 0
PCI
IOP
Attributes
Attributes
7
4
0
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+03EH