Intel CONTROLLERS 413808 - Manual (Page 771)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 771
Clocking and Reset—Intel ® 413808 and 413812
17.2.2 Software Reset
In addition to the fundamental resets, 81348 provides software control to reset the
internal bus, and Intel XScale
®
processor. Reset straps are not re-sampled due to
these resets.
• Internal Bus Reset Bit — This reset can be initiated in two ways. The first is by
writing to the coordinated reset bits in the MU Section 4.7.4, “Inbound Interrupt
Status Register - IISR” on page 414 . The second is via the watchdog timer as
described in Section 11.1.2, “Watch Dog Timer Operation” on page 629 . This reset
is specific to the integrated I/O processor and the associated peripheral units. PCI
Configuration Registers are preserved through this reset. See Section 17.2.8,
“Internal Bus Reset” for more details.
• Intel XScale
®
Processor Reset Bit — This reset is initiated through the
HOLD_X0_IN_RST# / HOLD_X1_IN_RST# straps, the ATUX Section 2.14.41,
“PCI Configuration and Status Register - PCSR” on page 178 , or the ATUE Section
3.17.41, “PCI Configuration and Status Register - PCSR” on page 327 . Once
invoked, the Intel XScale
®
processors are held in reset until released by software.
See Section 17.2.7, “Intel XScale® Processor Reset Mechanism” for more details.
• Targeted Core Reset — The Targeted Core reset can be used by an Intel XScale
®
processor to imitate a reset to another core in the system, including itself.
17.2.3 Secondary Bus Reset
When operating as a root complex or central resource, the following ‘secondary bus’
resets apply. Reset straps are not re-sampled due to these resets.
• PCI Express Hot Reset — When operating as a root complex, the ATUE can
generate the PCI Express Hot Reset sequence in order to reset the downstream
components on the PCI Express interface. This is accomplished by setting bit 0 of
the “PCI Express Link Control/Status Register - PELCSR” on page 334 in the
ATUE.( Section 3.17.45 )
• PCI Bus Reset — When operating as the central resource on the PCI/X bus, the
P_RSTOUT# output can be used to reset the downstream PCI bus. This is
accomplished by writing to bit 21 of the “PCI Configuration and Status Register -
PCSR” on page 178 in the ATUX ( Section 2.14.41 ). Bit 21 of PCSR defaults to a ‘1’.
It is the responsibility of the firmware to clear the Central Resource PCI Bus Reset
bit. After firmware clears bit 21 of PCSR hardware keeps the P_RSTOUT# signal
asserted (low) for about 300uS - the hardware waits about 150uS to allow the PLL
to warm-up and another 150uS to allow the clocks to stabilize. Therefore, firmware
has to wait about 300 uS after clearing bit 21 of PCSR. After the 300uS has
elapsed, hardware de-asserts the P_RSTOUT# signal. After P_RSTOUT#
de-asserts, firmware has to wait before issuing the first configuration cycle in order
to meet the PCI timing parameter Trhfa (about 2
26
PCI clocks). Note that the PCI
timing parameter Trhfa is dependent on the PCI bus speed selected.