Intel CONTROLLERS 413808 - Manual (Page 768)

Intel ® 413808 and 413812—Clocking and Reset
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
768 Order Number: 317805-001US
17.1.1.3 Clocking Region 3 (Internal Bus)
Region 3 covers the 81348 internal bus and obtains is input clock from either
REFCLK+/- or P_CLKIN defending on the setting of the CLK_SRC_PCIE# strap.
Region 3 operates at a frequency up to 400 MHz. All units interface to or reside in this
region. The units which interface to this region include the Intel XScale
®
processors,
the Memory Controller Unit, ATU and bridge to the AHB bus. Units which wholly reside
within region 3 include the Application DMA, XSI Bridge, SMBus interface, and
Peripheral Bus interface.
Region 3 contains an open-drain bi-directional clock (SMBCLK) used by the SMBus
interface. The SMBCLK operates at a maximum clock frequency of 100 KHz.
17.1.1.4 Clocking Region 4 (Peripheral Bus Interface)
Region 4 obtains its input clock from the clocking unit specified in region 3. This region
operates at a fixed 66 MHz and depending on the frequency of region 3 may be an
asynchronous boundary.
17.1.1.5 Clocking Region 5
Region 5 obtains its input clock from the clocking unit specified in region 3. This region
is used for low-speed peripheral units. Currently, this includes:
• I
2
C bus interface
• General-Purpose I/O unit
• UART serial bus interface
• Serial General-Purpose I/O unit
Region 5 contains an output clock (SCL) used for the I
2
C bus interface. The SCL clock
frequency is 100 KHz or 400 KHz. SCL is generated from the internal bus clock with its
frequency determined by the Fast Mode bit in the I2C Control Register x — ICRx . The
UART input clock is driven at 16.67 MHz, and divided within the unit for the serial
interface baud rate.
17.1.1.6 Clocking Region 7 (Intel XScale
®
Processor)
Region 7 obtains its input clock from either REFCLK+/- or P_CLKIN defending on the
setting of the CLK_SRC_PCIE# strap. This region is the Intel XScale
®
processor
(ARM* architecture compliant). It supports clock frequencies up to a maximum of 1200
MHz operation. The region 7 clock is an integer multiple of the Internal Bus clock
(region 3).