Intel CONTROLLERS 413808 - Manual (Page 195)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 195
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.57 ECC Control and Status Register - ECCCSR
The ECCCSR register provides additional information about ECC errors that occurred on
the PCI bus. Registers that store information from the failing transaction always store
information directly from the PCI bus (uncorrected), even when correction of the error
is possible.
Note: The “ECC Control and Status Register - ECCCSR” , “ECC First Address Register -
ECCFAR” , “ECC Second Address Register - ECCSAR” , and “ECC Attribute Register -
ECCAR” report the actual transaction that has the error. For example, when the Split
Completion of an original Outbound Read request has an error, the information
regarding the Split Completion is reported.
Table 84. ECC Control and Status Register - ECCCSR (Sheet 1 of 3)
Bit Default Description
31
0
2
(Mode 1 or
Conventional)
1
2
(Mode 2)
ECC Mode - When this bit is 1, the 4138xx is in ECC mode. When this bit is 0, the 4138xx is in parity
mode. The state of this bit after P_RST# is determined by the PCI-X initialization pattern described in
the PCI-X Protocol Addendum to the PCI Local Bus Specification, Revision 2.0. In PCI-X Mode 2, this bit
is a 1, otherwise this bit is a 0.
Note: The 4138xx does not support ECC in PCI-X Mode 1 or in Conventional PCI mode.
30 0
2
Disable Single-Bit-Error Correction - When the 4138xx is in ECC mode and this bit is 0, correctable
errors (as described in the PCI-X Protocol Addendum to the PCI Local Bus Specification, Revision 2.0)
are corrected. When the 4138xx is in ECC mode and this bit is 1, correctable errors are not corrected
and are treated as uncorrectable errors, including the setting of status bits and assertion of error
indicator signals on the bus. Disabling single-bit error correction enhances the error detection capability
of the ECC. In parity mode (ECC Mode bit is 0), this bit has no meaning and is ignored by the 4138xx.
Note: Writes to this register do not affect this bit unless the ECC Control Update Enable bit is a 1 in
the data pattern being written.
29 0
2
Reserved
28 0
2
ECC Control Update Enable - This bit always reads as a 0.
When this bit is 1 in the data pattern being written, the Disable Single-Bit-Error Correction and ECC
Mode bits are also updated (written). When this bit is 0 in the data pattern being written, the Disable
Single-Bit-Error Correction and ECC Mode bits are not updated.
27:24 0H
Error Upper Attributes - When the ECC Error Phase register is non-zero, this register indicates the
contents of the P_C/BE[3:0]# bus for the attribute phase of the transaction that included the error.
23:20 0H
Error Second Command - When the ECC Error Phase register is non-zero and the transaction that
included the error used a dual address cycle, this register indicates the contents of the P_C/BE[3:0]#
bus for the second address phase of the transaction that included the error.
19:16 0H
Error First (or only) Command - When the ECC Error Phase register is non-zero, this register indicates
the contents of the P_C/BE[3:0]# bus for the first (or only) address phase of the transaction that
included the error.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro
ro
rw
rw
rv
rv
wo
wo
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rv
rv
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
WO = Write Only
NA = Not Accessible
Internal Bus Address
+0D8H