Intel CONTROLLERS 413808 - Manual (Page 517)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 517
SRAM Memory Controller—Intel
®
413808 and 413812
8.3.2 SRAM Memory Interface Support
The 4138xx memory controller supports 1.0 Mbytes of on-chip SRAM. The SMCU
supports a 256-bit data bus width memory with ECC. The SMCU supports 7-bit ECC on
every 32-bit data quantity, providing higher performance when the core processor is
processing data by eliminating any RMW cycle required for 4-Byte store ECC
generation.
The SMCU supports seamless read/write bursting of long data streams.
8.3.2.1 SRAM Initialization
Initialization software should initialize the entire SRAM memory array in order to have
the correct ECC values for each ECC location. Refer to Section 8.3.3, “Error Correction
and Detection” on page 519 ) for more details. Reading from an uninitialized memory
location will result in an ECC error. By default data parity checking is disabled, firmware
must enable data parity checking if required. Refer to Section 357, “SRAM Parity
Control and Status Register — SPARCSR” on page 542 .
8.3.2.2 SRAM Read Sequence
Read transactions require ECC codes to be calculated and compared with the ECC
returned by the SRAM array. The following steps describe the read sequence.
1. Each of the SMCU inbound memory transaction ports decodes the address to
determine if the transaction should be claimed.
— If the address falls in the SRAM address range indicated by the SRAMBAR and
SRAMUBAR the SMCU claims the transaction.
2. Once the SMARB selects the highest priority port transaction, it forwards the
transaction to the SRAM control block.
3. Upon receipt of the data, the SRAM Control Block calculates the ECC code from the
data and compares it with the ECC returned by the SRAM array. Section 8.3.3,
“Error Correction and Detection” on page 519 explains the ECC algorithm in more
detail.
4. Assuming the calculated ECC matches the read ECC, the SRAM Control Block drives
the data back to the corresponding memory port.
— For each burst read issued, the memory controller increments the address by
sixteen.
The SMCU continues to return data to the corresponding memory port based on the
byte count of the transaction.