Intel CONTROLLERS 413808 - Manual (Page 128)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
128 Order Number: 317805-001US
2.10.2 Accessing Vital Product Data
The VPD Capabilities List Item provides three fields which the system uses to access
the Vital Product Data:
VPD Address DWORD Aligned Byte address of the VPD to be accessed which
is represented by VPDAR[14:0]. Note that this means that the
maximum size of the VPD is 128 Kbytes. The user may pick any
128 Kbyte block of memory in the storage component for the
VPD.
Flag The flag register is used to indicate when the transfer between
the VPD Data Register and the storage component is completed.
The flag is in VPDAR[15] which means that the Flag is written at
the same time that VPD address is written.
VPD Data Four bytes of VPD Data can be read or written through this field
which is represented by VPDDR[31:0]. The least significant byte
of this register represents the byte at the VPD Address
(VPDAR[14:0]). Four bytes are always transferred between this
register and the VPD storage component.
2.10.2.1 Reading Vital Product Data
Using the fields defined in the VPD Capabilities List Item, the 4138xx reads Vital
Product Data using the following sequence of events:
1. Host processor executes a configuration write of the VPD address to the VPDAR
with the Flag cleared.
2. An interrupt to the Intel XScale
®
processor is triggered and bit 17 of the ATUISR is
set. Meanwhile, the host processor polls the VPDAR register waiting for the Flag to
be set.
Warning:
When any configuration writes to either the VPDAR or the VPDDR occur prior to the Flag
being set, the results of the original read operation are unpredictable.
3. Using the VPD Address, the Intel XScale
®
processor retrieves the Vital Product
Data from the VPD storage component (i.e., Flash Memory).
4. The Intel XScale
®
processor then writes this data to VPD Data Register (VPDDR).
5. The Intel XScale
®
processor clears the VPD interrupt status bit in the ATUISR.
6. The Intel XScale
®
processor then sets the Flag in the VPDAR register.
7. When the host processor detects that the Flag has been set, the host processor
then reads the retrieved VPD from the VPDDR.