Intel CONTROLLERS 413808 - Manual (Page 270)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
270 Order Number: 317805-001US
3.9 ATU Error Conditions
PCI Express and internal bus error conditions cause ATU to log header information and
set status bits to inform error handling code of exact cause of error condition. Two sets
of registers are provided to allow independent control by both the Host processor and
the internal Intel XScale
®
microarchitecture. Error conditions and status can be found
in the ATUSR. The basic flow for a PCI Express error is as follows:
• Log the Error in the PCI Express Advanced Error and the PCI Interface Error
registers
• Set the bit in the ATU Status Register which corresponds to the error condition
(master abort, target abort, etc.)
• Set the bit in the ATU Interrupt Status Register which corresponds to the error
condition (master abort, target abort, etc.). This function is maskable for all PCI
error conditions.
• The setting of the bit in the ATU Interrupt Status Register results in an interrupt
being driven to the Intel XScale
®
processor.
Error conditions on one side of the ATU are generally propagated to the other side of
the ATU and have different effects depending on the error. Error conditions and their
effects are described in the following sections.
PCI Express error conditions and the action taken on the link are defined within the PCI
Express Base Specification, Revision 1.0a. The ATU adheres to the error conditions
defined within the PCI specification for both requester and completer operation. Error
conditions on the internal bus are caused by an ECC error from the Memory Controller,
(see Section 8.4, “ECC Interrupts/Error Conditions” on page 531 for details on memory
controller error conditions), an Internal Bus Byte Parity Error, or by incorrect
addressing resulting in an internal master abort or target abort. All actions on the PCI
Express interface for error situations are dependent on the error control bits found in
the ATU Command Register ( Section 3.17.5, “ATU Command Register - ATUCMD” on
page 298 ), the PCI Express Device Control Register ( Section 3.17.59, “PCI Express
Device Control Register - PE_DCTL” on page 344 ) and the PCI Express Advanced Error
Masks ( Section 3.17.71, “PCI Express Uncorrectable Error Mask - ERRUNC_MSK” on
page 356 and Section 3.17.74, “PCI Express Correctable Error Mask - ERRCOR_MSK”
on page 359 ).
The following sections detail all ATU error conditions on the PCI Express and 4138xx
internal bus, action taken on these conditions, and status and control bits associated
with error handling.