Intel, Bit default description, Pmon – Intel CONTROLLERS 413808 User Manual
Page 752
Intel
®
413808 and 413812—PMON Unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
752
Order Number: 317805-001US
14:12
000b
Command Trigger Source Select (CTSS)
This field expands the Event Selection Codes in the Command trigger field to 1 of 8 ports, which share
the same codes. Normally driven to 000, unless another source of the same type is to be selected. For
4138xx, there are 8 different sources for SAS/SATA events, so setting these bits as “000” choose an
event from SAS/SATA Port-0, and setting these bits as “001” choose an event from SAS/SATA Port-1,
etc.
11:0
000h
Command Trigger (CT)
This field contains the Event Selection Code (ESC) that the unit is required to detect before executing
the opcode. The previously programmed opcode continues to execute until this command trigger is
detected.
The ESC of 000h (the default value) is a special case, This special ESC causes the command to be
triggered immediately upon being written to the command register. The special command trigger also
causes that command to be executed (triggered) once and only once. All other (non-0) ESCs cause the
command to be re-executed every time the trigger is detected. Refer to the Event tables for valid
values. For the Stop, Start, and Reset opcodes, re-executing every time the trigger is detected is
meaningless. For other opcodes, care must be taken to prevent the CT from producing undesirable
behavior. The only opcodes that are anticipated as being useful with continual triggering include the
Restart functionality which behavior is necessary to facilitate gathering of histogram data at hardware
speeds.
Only one trigger can occur per core clock. When the trigger source clock is running faster than the core
clock and more than one trigger event occurs per core clock, these additional triggers are dropped.
See the Event Table for valid values.
Table 492. PMON Command Register 0-7 - PMON_CMD[0:7] (Sheet 4 of 4)
Bit
Default
Description
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
PMON
_CMD0
PMON
_CMD1
PMON
_CMD2
PMON
_CMD3
PMON
_CMD4
PMON
_CMD5
PMON
_CMD6
PMON
_CMD7
+000h
+010h
+020h
+030h
+040h
+050h
+060h
+070h