Intel CONTROLLERS 413808 - Manual (Page 41)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 41
Introduction—Intel
®
413808 and 413812
1.3 About This Document
This document is the authoritative and definitive reference for the external architecture
of the Intel
®
413808 and 413812 I/O Controllers in TPER Mode (4138xx), with Intel
XScale
®
microarchitecture
2
.
Intel Corporation assumes no responsibility for any errors which may appear in this
document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without
notice. In particular, descriptions of features, timings, packaging, and pin-outs does not
imply a commitment to implement them. In fact, this specification does not imply a
commitment by Intel to design, manufacture, or sell the product described herein.
1.3.1 How To Read This Document
This document describes the product-specific features of the 4138xx. Each chapter
describes a different feature and starts with an overview followed by the theory of
operation.
The reader should have a working understanding of the Peripheral Component
Interconnect (PCI) Local Bus Specification, the PCI-X Addendum to the PCI Local Bus
Specification and the PCI Express Specification. For more information, refer to the PCI
Local Bus Specification, Revision 2.3, the PCI-X Addendum to the PCI Local Bus
Specification, Revision 2.0a, and the PCI Express Specification, Revision 1.0a.
1.3.2 Other Relevant Documents
1. Intel
®
80200 Processor based on Intel
®
XScale™ Microarchitecture Developer’s
Manual (Order Number: 273411), Intel Corporation
2. PCI Local Bus Specification, Revision 2.3 - PCI Special Interest Group
3. PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Special
Interest Group
4. PCI Express Specification, Revision 1.0a - PCI Special Interest Group
2. ARM architecture compliant.