Intel CONTROLLERS 413808 - Manual (Page 639)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 639
Timers—Intel ® 413808 and 413812
11.4.6 Watch Dog Timer Control Register – WDTCR
The Watch Dog Timer Control Register (WDTCR) is a 32-bit register that software can
use to enable the WDT or read the current WDT count value. The register value
decrements with each internal bus clock tick. When this register value decrements to
zero (terminal count), an Internal Bus Reset or an interrupt is generated. Refer to
Section 426, “Watch Dog Timer Setup Register — WDTSR” on page 639 .The timer can
be enabled and/or reinitialized by writing 1E1E 1E1EH immediately followed by
E1E1 E1E1H to the WDTCR. Once enabled, the WDT can be disabled by writing
1F1F 1F1FH immediately followed by F1F1 F1F1H to the WDTCR.
Note: This register is also controlled by the TMR1.pri (TMR1[3]) bit. For example, it can be
written only by privileged processes.
11.4.7 Watch Dog Timer Setup Register – WDTSR
The Watch Dog Timer Setup Register (WDTSR) is a 32-bit register that software can
use to select the action taken when the WDT register value decrements to zero
(terminal count) — either an interrupt or an internal bus reset can be generated.
Note: This register is also controlled by the TMR1.pri (TMR1[3]) bit. For example, it can be
written only by privileged processes.
Table 425. Watch Dog Timer Control Register — WDTCR
31:00 0000 0000H
Watch Dog Timer Count Value — By writing 1E1E 1E1EH followed by E1E1 E1E1H to this register,
software can enable the WDT and reset the count value to FFFF FFFFH. When read, this register
returns the current value contained in the WDT. Once enabled, the WDT can be disabled by writing
1F1F 1F1FH immediately followed by F1F1 F1F1H to the WDTCR
MMR
CP
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor
Coprocessor address
WDTCR: CP6, Page 9, Register 7
Table 426. Watch Dog Timer Setup Register — WDTSR
31 0
2
Preserved.
30:01 0000 000H Reserved.
00 0
2
Watch Dog Timer Event Selector bit — This bit selects whether the WDT generates an interrupt or an
internal bus reset when the WDT register value decrements to zero (terminal count). When an
interrupt is chosen, the interrupt is posted in the Timer Interrupt Status Register (TISR). Refer to
Section 424, “Timer Interrupt Status Register – TISR” on page 638 .
0 = An interrupt is generated
1 = A reset is generated
MMR
CP
28 24 20 16 12 8 4 0 31
pr rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor
address
WDTSR: CP6, Page 9, Register 8