Intel CONTROLLERS 413808 - Manual (Page 568)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
568 Order Number: 317805-001US
10.3.3 Exception Priorities and Vectors
It is important to note that fast interrupt (FIQ) is higher priority than the normal
interrupt (IRQ). In addition, while an FIQ exception is executing, the IRQ exception is
masked out.
When an exception is taken by the processor, the Program Counter (PC) is loaded with
the vector associated with that exception as specified by Table 376 .
Generally, the instruction at this location is required to be a branch instruction to the
associated exception handler. However, in the case of an FIQ, this is not necessary
since the vector location is at the very bottom of all the defined exception vectors, thus
the entire FIQ exception handler can be placed at that vector location.
10.3.4 Software Requirements For Exception Handling
To use the processor’s exception handling facilities, user software must provide the
following items in memory:
• Exception Handler Routines
• Software handler to nest certain exceptions (i.e., FIQ and IRQ)
These items are established in memory as part of the initialization procedure.
10.3.4.1 Nesting FIQ and IRQ Exceptions
Hardware does not provide support for nesting of any particular exception, including
the FIQ and IRQ exceptions.
In order to provide support for nested interrupts, a software handler must be provided
to save the Link Register (R14) and the SPSR (Saved Program Status Register) before
reenabling the FIQ or IRQ exception.
Table 376. Exception Priorities And Vectors
Exception Priority Vector
a
a. By enabling the Exception Vector Relocation mode (bit 13, CP15, Register 1), the Vectors (except Reset
Vector) can be relocated to be based at FFFF 0000H rather than 0000 0000H. (i.e., FIQ Vector located at
FFFF 001CH)
Reset 1 (Highest) 0000 0000H
Data Abort 2 0000 0010H
FIQ 3 0000 001CH
IRQ 4 0000 0018H
Prefetch Abort 5 0000 000CH
Undefined Instructions 6 (Lowest) 0000 0004H
Software Interrupt (SWI) b
b. Undefined Instruction and SWI can not occur at the same time since SWI is a particular instruction decoding.
6 (Lowest) 0000 0008H