Intel CONTROLLERS 413808 - Manual (Page 218)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
218 Order Number: 317805-001US
2.14.79 Outbound Configuration Cycle Address Register - OCCAR
The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI
configuration cycle address. The Intel XScale
®
processor writes the PCI configuration
cycles address, which enables outbound configuration read or write. The Intel XScale
®
processor then performs a read or write to the Outbound Configuration Cycle Data
Register to initiate the configuration cycle on the PCI bus.
Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined
differently for Conventional versus PCI-X modes. When 4138xx software programs the
OCCAR to initiate a Type 0 configuration cycle, the OCCAR should always be loaded
based on the PCI-X definition for the Type 0 configuration cycle address. When
operating in Conventional mode, the 4138xx clears bits 15:11 of the OCCAR prior to
initiating an outbound Type 0 configuration cycle. See the PCI-X Protocol Addendum to
the PCI Local Bus Specification, Revision 2.0 for details on the two formats.
Table 106. Outbound Configuration Cycle Address Register - OCCAR
Bit Default Description
31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound
configuration read or write cycle.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+330H