29 inbound atu translate value register 0 - iatvr0, 29inbound atu translate value register 0 - iatvr0, Address translation unit (pci express)—intel – Intel CONTROLLERS 413808 User Manual

Page 319: Bit default description, Intel

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413808 and 413812 I/O Controllers in TPER Mode

October 2007

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319

Address Translation Unit (PCI Express)—Intel

413808 and 413812

3.17.29 Inbound ATU Translate Value Register 0 - IATVR0

The Inbound ATU Translate Value Register 0 (IATVR0) in conjunction with the

“Inbound

ATU Upper Translate Value Register 0 - IAUTVR0” on page 319

contain bits 35 to 12 of

the internal bus address used to convert PCI Express Link addresses. The converted

address is driven on the internal bus as a result of the inbound ATU address translation.

3.17.30 Inbound ATU Upper Translate Value Register 0 - IAUTVR0

The Inbound ATU Upper Translate Value Register 0 (IAUTVR0) in conjunction with the

“Inbound ATU Translate Value Register 0 - IATVR0” on page 319

contain bits 35 to12 of

the internal bus address used to convert PCI Express Link addresses. The converted

address is driven on the internal bus as a result of the inbound ATU address translation.

Table 169. Inbound ATU Translate Value Register 0 - IATVR0

Bit

Default

Description

31:12

FF000H

Inbound ATU Translation Value 0 - This value represents bits 31 to 12 of the internal bus address used

to convert the PCI address to internal bus addresses. This value must be naturally aligned with the

IABAR0 register’s programmed value (see

Section 3.17.15, “Determining Block Sizes for Base

Address Registers” on page 306

).The default address allows the ATU to access the internal 4138xx

memory-mapped registers.

11:01

000H

Reserved

Big Endian Byte Swap enable - When set the ATU performs a byte swap on all PCI read/write

transactions through BAR0. When clear, no swap is performed. Refer to

Section 3.4, “Big Endian Byte

Swapping” on page 255

for more details.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+044H

Table 170. Inbound ATU Upper Translate Value Register 0 - IAUTVR0

Bit

Default

Description

31:04

000 0000H Reserved

3:0

Inbound Upper ATU Translation Value 0 - This value represents bits 35 to 32 of the internal bus address

used to convert the PCI address to internal bus addresses. The default address allows the ATU to access

the internal 4138xx