Intel CONTROLLERS 413808 - Manual (Page 784)

Intel ® 413808 and 413812—Test Logic Unit and Testability
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
784 Order Number: 317805-001US
18.2.1 TAP Pin Description
The internal test logic is accessed through the TAP pins. The following sections describe
some of the rules and permissions of the IEEE 1149.1a Standard for the TAP pins.
18.2.1.1 Test Clock (TCK)
This is the clock input for the test logic defined by this standard, i.e. the TAP controller
and associated registers. The TLU is a fully static design, thus all registers retain their
states indefinitely when TCK is stopped at “0” or “1”.
18.2.1.2 Test Mode Select (TMS)
This pin is used to control the operation of the TAP controller. The signal received at
TMS is decoded by the TAP controller to control test operations. The state of TMS is
sampled on the rising edge of TCK . Internally, there is a weak pull-up on this pin to
provide a logic high when not driven, per standard definition.
18.2.1.3 Test Data Input (TDI)
This pin is used to provide serial input data to the instruction and test data registers.
Data at TDI is sampled on the rising edge of TCK . Data shifted from TDI through a
register to TDO appears non-inverted at TDO after a number of rising and falling edges
of TCK determined by the length of the instruction or test data register selected.
Internally, there is a weak pull-up on this pin to provide a logic high when not driven,
per standard definition.
18.2.1.4 Test Data Output (TDO)
This is the serial data output pin. Changes in the state of TDO occur only following the
falling edge of TCK while performing a shift operation. This pin is only driven while
scanning (in SHDR or SHIR states) otherwise it is in inactive (high Z) state. The
non-shift inactive state is provided to support parallel connection of TDO outputs at the
board or module level.
18.2.1.5 Asynchronous Reset (TRST#)
The TRST# signal is used to asynchronously reset the TAP controller and
boundary-scan registers. The TAP controller is not initialized by any other system input,
including system reset. The TAP controller initializes asynchronously on the falling edge
of TRST# to the Test-Logic_Reset (initial) state. The TAP controller is initialized at
power-up by cirrostrati built into the test logic. Upon reset, the TAP instruction register
initializes to the IDCODE instruction. Internally, there is a weak pull-up on this pin to
provide a logic high when not driven.