Intel CONTROLLERS 413808 - Manual (Page 545)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 545
Peripheral Bus Interface Unit—Intel
®
413808 and 413812
9.0 Peripheral Bus Interface Unit
This chapter describes the Peripheral Bus Interface Unit (PBI) of the Intel
®
413808 and
413812 I/O Controllers in TPER Mode (4138xx). It explains the following:
• Peripheral Bus signals, which consist of address/data, control/status
• Peripheral Bus Read, and write transactions
• Peripheral Bus configuration and Flash Memory Support
• Registers
This chapter also serves as a starting point for the hardware designer when interfacing
typical flash components to the 4138xx Peripheral Bus.
Figure 62. The Peripheral Bus Interface Unit
16-Bit I/F I 2 C Bus
South
Bridge
Host Interface
Three I 2 C
Bus
Interfaces
APB
PBI
Unit
(Flash)
SMBus
Unit
SMBus
128-Bit South Internal Bus PCI-X or PCI-E
B6265-01