Intel CONTROLLERS 413808 - Manual (Page 458)

Intel
®
413808 and 413812—SGPIO Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
458 Order Number: 317805-001US
6.0 SGPIO Unit
Note: For TPER mode the register interface defined here can be used. For Intel
®
413808 and
413812 I/O Controllers (4138xx) non-TPER mode, see the SAS/SATA Command
Summary for API to control the SGPIO units. Some limitations may apply when
controlling via the API.
6.1 Overview
This section describes Serial General Purpose Input Output (SGPIO) interface. The
4138xx (based on Intel XScale
®
technology
14
) supports two SGPIO interfaces. The
SGPIO is a serial bus consisting of four signals:
• SClock
• SLoad
• SDataOut
• SDataIn
The SGPIO is used to serialize general purpose I/O signals. The SGPIO defines
communication between an initiator and a target. The target typically converts output
signals into multiple parallel LED signals and provides inputs frsom general purpose
inputs. Figure 43 shows the SGPIO bus. A target typically consists of multiple devices,
and SGPIO protocol allows each device on the target to support up to three output and
three input signals.
Each SGPIO interface on 4138xx can support up to eight devices (drives) on the target
end. Each device can control up to three output bits and three input bits. Therefore,
each SGPIO interface on 4138xx can support up to twenty-four input signals and
twenty-four output signals. Some usage models require both SGPIO units on 4138xx to
be used in conjunction with each other.
For example, when using direct LED support for eight drives, both SGPIO units have to
used together, as one SGPIO can only support up to four drives for direct LED.
14.ARM architecture compliant.