Intel CONTROLLERS 413808 - Manual (Page 45)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 45
Introduction—Intel
®
413808 and 413812
1.5.3 Internal Busses
The 4138xx is architected around two internal busses: north internal bus and south
internal bus. The two busses use the same bus protocol. The north internal bus is
128-bit wide and operates at speed up to 400 MHz.
The south internal bus is 128-bits wide and operates at speeds up to 400 MHz. The
south internal bus provides data paths for large DMA generated burst transactions.
Both the internal address and data busses on the south internal bus are parity
protected on a byte-wise basis.
1.5.4 Application DMA Controller
ADMA is not available in the 4138xx in any mode.
1.5.5 Address Translation Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to the local
memory. The ATU provides the interface for the RAID Controller PCI function. The ATU
supports transactions between PCI address space and the internal address space.
Address translation is controlled through programmable registers accessible from both
the PCI interface and the Intel XScale
®
processor. Dual access to registers allows
flexibility in mapping the two address spaces. The ATU also supports the extended
capability configuration headers.