Intel CONTROLLERS 413808 - Manual (Page 720)

Intel ® 413808 and 413812—I 2 C Bus Interface Units
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
720 Order Number: 317805-001US
14.8.4 I
2
C Data Buffer Register
x —
IDBR
x
The I
2
C Data Buffer Register (IDBRx) is used by the 4138xx to transmit and receive
data from the I
2
C bus. The accesses the IDBRx by the 4138xx on one side and by the
I
2
C shift register on the other. Data coming into the I
2
C Bus Interface Unit is received
into the IDBRx after a full byte has been received and acknowledged. Data going out of
the I
2
C Bus Interface Unit is written to the IDBRx by the Intel XScale
®
processor and
sent to the serial bus.
When the I
2
C Bus Interface Unit is in transmit mode (master or slave), the 4138xx
writes data to the IDBRx over the internal bus. This occurs when a master transaction
is initiated or when the IDBRx Transmit Empty Interrupt is signalled. Data is moved
from the IDBRx to the shift register when the Transfer Byte bit is set. The IDBR
Transmit Empty Interrupt is signalled (when enabled) when a byte has been transferred
on the I
2
C bus and the acknowledge cycle is complete. When the IDBRx is not written
by the 4138xx (and a STOP condition was not in place) before the I
2
C bus is ready to
transfer the next byte packet, the I
2
C Bus Interface Unit inserts wait states until the
Intel XScale
®
processor writes the IDBRx and sets the Transfer Byte bit.
When the I
2
C Bus Interface Unit is in receive mode (master or slave), the processor
reads IDBRx data over the internal bus. This occurs when the IDBRx Receive Full
Interrupt is signalled. The data is moved from the shift register to the IDBRx when the
Ack cycle is complete. The I
2
C Bus Interface Unit inserts wait states until the IDBR has
been read. Refer to Section 14.3.2, “I2C Acknowledge” on page 699 for acknowledge
pulse information in receiver mode. After the 4138xx reads the IDBRx, the Ack/Nack
Control bit is written and the Transfer Byte bit is written, allowing the next byte transfer
to proceed on the I
2
C Bus. The IDBRx register is 00H after reset.
Table 474. I
2
C Data Buffer Register x — IDBRx
Bit Default Description
31:08 000000H Reserved
07:00 00H I 2 C Data Buffer : Buffer for I 2 C bus send/receive data.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Unit #
0
1
2
Intel XScale ® processor internal bus address
offset
+250CH
+252CH
+254CH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible