5 pbi limit register 0 - pblr0, Table 368. pbi limit register 0 - pblr0, 5 pbi limit register 0 — pblr0 – Intel CONTROLLERS 413808 User Manual
Page 558: 368 pbi limit register 0 — pblr0, Intel, Bit default description, Processor local bus address, 158ch
Intel
®
413808 and 413812—Peripheral Bus Interface Unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
558
Order Number: 317805-001US
9.3.5
PBI Limit Register 0 — PBLR0
The 4138xx limit register’s (PBLR0) programmed value must be naturally aligned with
the base address register’s (PBBAR0) programmed value. The limit register is used as a
mask when the address decode for memory window 0 is performed.
.
Table 368. PBI Limit Register 0 — PBLR0
Bit
Default
Description
31:12
FE000H
Memory Window 0 Limit: This value determines the memory block size required for the Memory Window
0. Defaults to an 32MB Peripheral Window
11:00
000H
Reserved
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale
®
processor Local Bus Address
Offset
+158CH