Intel CONTROLLERS 413808 - Manual (Page 408)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
408 Order Number: 317805-001US
To signal an Outbound Interrupt with MSI-X enabled, the 4138xx creates an outbound
write transaction using the Message Address and the Message Data of the associated
entry. On 4138xx, entry 0 of the MSI-X Table is assigned to bit OISR[0], entry 1 is
assigned to bit OISR[1] and so on. For example, entry 7 of the MSI-X Table is assigned
to bit OISR[7].
Note: Entry 2 is assigned to bits OSIR[2] and OISR[31]. For example, the Outbound Doorbell
Register and the Firmware Interrupt bit in the Outbound Control and Status Register.
Note: When host software enables MSI, a Messaging Unit Interrupt does not result in the
assertion of the P_INTx# output pin. However, all the P_INT[A:D]# pins are
functional for steering of interrupts from other PCI devices that may not be MSI
capable.
MSI-X Table and Pending Bits Array are mapped relative to the PCI/Host interface
( Figure 41 ). The MU registers are located in the first 4-KByte of the 8-KByte address
space claimed by the MU, whereas the MSI-X Table is located at a 4-KByte offset and
the MSI-X PBA is located at a 6-KByte offset relative to the MU Base Address. Note that
the MU Base Address register must be programmed such that it overlaps the address
space defined by the ATU Translate and ATU Limit Registers. For example, the MU
8-KByte window must overlap onto the ATU Translation Window.
Figure 41. MSI-X Table and PBA Address Mapping Layout relative to the Host Interface
MU Registers
8 KBytes
MU BAR
4 KB
MSI-X PBA
MSI-X Table
4 KB
2 KB
2 KB
NOTE: MU space must overlap the ATU Translation Window.
B6216-01