9 bridge error control and status register - becsr, 9 bridge error control and status register — becsr, Bridge error control and status register — becsr – Intel CONTROLLERS 413808 User Manual
Page 508: Intel, Bit default description, Requester id
Intel
®
413808 and 413812—System Controller (SC) and Internal Bus Bridge
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
508
Order Number: 317805-001US
7.5.9
Bridge Error Control and Status Register — BECSR
The BECSR logs the type of error that the bridge encountered on either north or south
interface. Only one error can be logged at a time.
The Bridge has two interrupt conditions: first Bridge error (BECSR[0]), and more than
one Bridge error (BECSR[1]).
When the Bridge detects an error and BECSR[0] is cleared, the error is logged in
BECSR, and BECSR[0] is set to 1. When BECSR[0] is not cleared, any additional Bridge
errors are not logged and BECSR[1] is set.
Table 342. Bridge Error Control and Status Register — BECSR (Sheet 1 of 2)
Bit
Default
Description
31:17
0000H
Reserved.
16
0
2
Error Reporting Enable: This bit when set enables the internal bus bridge to signal an interrupt to the
Intel XScale
®
processor when a South Internal Bus Error is detected. When cleared, an interrupt to the
Intel XScale
®
processor is not signaled when a South Internal Bus Address Error is detected
Note:
This enable applies to all error types reported by the Internal Bus bridge through BECSR[3:2]
15:12
0H
Reserved.
11:08
0H
This field logs the Requester ID of the transaction that resulted in an error.
Requester ID
Core 0
1
Core 1
2
ATU-X
3
ATU-E
4
Reserved
5
N/A
6
LMU
7
N/A
8
SMBus
9
07:06
00
2
Reserved.
05
0
2
Interface Type: This bit indicates the Bridge interface that encountered the error condition.
0 = North Internal Bus Interface.
1 = South Internal Bus Interface
04
0
2
Command Type: Indicates the command type that encountered the error:
0 = Read.
1 = Write.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rv
na
rv
na
rv
na
rv
na
ro
na
ro
na
ro
na
ro
na
rv
na
rv
na
ro
na
ro
na
ro
na
ro
na
rc
na
rc
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
South XBG
internal bus address offset
+178CH