Intel CONTROLLERS 413808 - Manual (Page 55)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 55
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.2.1 Inbound Transactions
Inbound transactions which target the ATU are translated and executed on the 4138xx
internal bus. As a PCI target, the ATU is capable of accepting all PCI memory read and
write operations as either a 32-bit or a 64-bit PCI target. In the conventional PCI mode
Memory Write and Memory Write and Invalidate operations are performed as posted
operations and all memory read operations are performed as delayed reads. In the
PCI-X mode Memory Write, Memory Write Block, and Alias to Memory Write Block
operations are performed as posted operations and Memory Read DWORD, Memory
Read Block, and Alias to Memory Read Block operations are executed as split
transactions. The ATU is capable of accepting configuration read and write cycles. In
the conventional PCI mode, Configuration Writes are performed as delayed memory
write operations and Configuration Reads are performed as delayed read operations. In
the PCI-X mode, both Configuration Writes and Configuration Reads are performed as
split transactions.
Inbound memory write transactions have their addresses entered into the inbound
write address queue (IWADQ) and data entered into the inbound write data queue
(IWQ). The IWQ/IWADQ pair are capable of holding up to 4 write operations up to the
size of the data queue. Inbound configuration writes use the inbound delayed write
queue (IDWQ) for address and data. Refer to Section 2.6 for details of queue
operation. Inbound read operations (memory and configuration) have their address
entered into the inbound transaction queue (ITQ) and the data is returned to the PCI
master in the inbound read queue (IRQ). The ITQ is capable of holding up to 8 delayed
read requests (split read requests when operating in the PCI-X mode).
In the conventional PCI mode, for inbound transactions, the ATU is a slave on the PCI
bus and is a requester on the internal bus. PCI slave operation is defined in the PCI
Local Bus Specification, Revision 2.3. In the PCI-X mode, for inbound transactions, the
ATU initially is a target on the PCI bus and becomes an initiator when performing split
completion transactions, and is an initiator on the internal bus.
Operation of the internal bus is defined in
Chapter 7.0, “System Controller (SC) and
Internal Bus Bridge” . Specific operation of the ATU as master on the internal bus is
defined in Section 2.2.6 .