Intel CONTROLLERS 413808 - Manual (Page 107)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 107
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.4 Correctable Data Errors on the PCI Interface
When the 4138xx PCI interface is operating in Mode 2 and Single-Bit Correction is
enabled, correctable data errors may occur on the PCI bus.
Two kinds of correctable data errors can occur on the PCI interface: errors as an
initiator and errors as a target.
Errors encountered as an initiator:
— Outbound Read Request
— Outbound Write Request
— Inbound Read Completions
— Inbound Configuration Write Completion Messages
As an initiator, the ATU provides no error response for correctable data errors.
Errors encountered as a target:
— Inbound Read Request (Immediate Data Transfer)
— Inbound Write Request
— Outbound Read Completions
— Inbound Configuration Write
— Split Completion Messages
As a target, the ATU provides an error response for correctable data errors on inbound
writes, outbound read completions, inbound configuration writes, and split completion
messages. However, the ATU provides no error response for correctable data errors on
inbound read requests.
In general, when the ATU is receiving data from the PCI bus as a target, any
correctable data errors are corrected and logged. Otherwise, the ATU functions as when
no error had occurred.
2.7.4.1 Inbound Read Request Correctable Data Errors
2.7.4.1.1 Immediate Data Transfer
As a target device in this scenario, no action is required and no error bits are set.
2.7.4.1.2 Split Response Termination
As a target device in this scenario, no action is required and no error bits are set.
2.7.4.2 Inbound Write Request Correctable Data Errors
As a target device, when an inbound write request correctable data error is detected,
the following actions are taken:
• Error is corrected and ATU completes the transaction on the PCI bus as when no
error had occurred. Then, the transaction is normally forwarded to the internal bus.
• Update “ECC Control and Status Register - ECCCSR” on page 195 , “ECC First
Address Register - ECCFAR” on page 198 , “ECC Second Address Register - ECCSAR”
on page 199 , and “ECC Attribute Register - ECCAR” on page 200 for transaction.
— When ATU Detected Correctable Error Interrupt Mask bit in the ATUIMR is clear,
set the Detected Correctable Error bit in the ATUISR. When set, no action.