Intel CONTROLLERS 413808 - Manual (Page 208)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
208 Order Number: 317805-001US
2.14.69 Outbound I/O Base Address Register - OIOBAR
The OIOBAR register locates the 64 KB I/O cycle address window in the 4138xx’s
64 Gbyte internal address space. When A[35:16] of the internal bus address matches
the value in OIOBAR, the ATU claims the transaction and forward it over to the PCI
interface as an I/O cycle.
Note: In translating the internal bus address A[35:0] for the PCI bus I/O cycle, A[15:0] is
forwarded over to the PCI bus unmodified while A[31:16] is set to 0000H. (see “I/O
Transactions” on page 71 ).
Table 96. Outbound I/O Base Address Register - OIOBAR
Bit Default Description
31:12 0 FFFBH
Outbound I/O Base Address - This value represents bits 35 to 16 of the internal bus address used to
claim an outbound I/O cycle request for the ATU.
11:3 000H Reserved
2:0 0H
Outbound I/O Function Number Mapping - The Function number in this field is used as part of the
Requestor ID for outbound I/O transactions
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+300H