Intel CONTROLLERS 413808 - Manual (Page 505)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 505
System Controller (SC) and Internal Bus Bridge—Intel
®
413808 and 413812
7.5.6 Bridge Window Base Address Register — BWBAR
The Bridge Base Address Register (BWBAR) defines the block of memory addresses
where the Bridge Memory Window begins. The BWBAR is used in conjunction with the
BWLR to form a memory window that is used by the Bridge to claim transactions on the
South Internal Bus. The BWBAR defines the base address and describes the required
memory block size; see Section 7.5.5, “Determining Block Sizes for Memory Windows”
on page 504 . The selected base address needs to be naturally aligned to the granularity
of the memory block size. For instance, when a 64 Kbyte memory window size is
selected, the base address needs to be 64 Kbyte address aligned (i.e., bits 15:12 of the
base address are required to be 000b).
Table 339. Bridge Window Base Address Register — BWBAR
Bit Default Description
31:12 FFE0 0H
Bridge Memory Window Base Address: These bits define the actual location the Bridge responds to
for accesses to the Bridge Memory Window on the South Internal Bus.
11:00 000H Reserved.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Local Bus Address
Offset
+1780H South XBG