Intel CONTROLLERS 413808 - Manual (Page 144)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
144 Order Number: 317805-001US
048H Section 2.14.30, “Inbound ATU Upper Translate Value Register 0 - IAUTVR0” on page 170
04CH Section 2.14.31, “Inbound ATU Limit Register 1 - IALR1” on page 171
050H Section 2.14.32, “Inbound ATU Translate Value Register 1 - IATVR1” on page 172
054H Section 2.14.33, “Inbound ATU Upper Translate Value Register 1 - IAUTVR1” on page 172
058H Section 2.14.34, “Inbound ATU Limit Register 2 - IALR2” on page 173
05CH Section 2.14.35, “Inbound ATU Translate Value Register 2 - IATVR2” on page 174
060H Section 2.14.36, “Inbound ATU Upper Translate Value Register 2 - IAUTVR2” on page 174
064H Section 2.14.37, “Expansion ROM Limit Register - ERLR” on page 175
068H Section 2.14.38, “Expansion ROM Translate Value Register - ERTVR” on page 176
06CH Section 2.14.39, “Expansion ROM Upper Translate Value Register - ERUTVR” on page 176
070H Section 2.14.40, “ATU Configuration Register - ATUCR” on page 177
074H Section 2.14.41, “PCI Configuration and Status Register - PCSR” on page 178
078H Section 2.14.42, “ATU Interrupt Status Register - ATUISR” on page 181
07CH Section 2.14.43, “ATU Interrupt Mask Register - ATUIMR” on page 183
080H — 08FH Reserved
090H Section 2.14.44, “VPD Capability Identifier Register - VPD_Cap_ID” on page 185
091H Section 2.14.45, “VPD Next Item Pointer Register - VPD_Next_Item_Ptr” on page 185
092H Section 2.14.46, “VPD Address Register - VPDAR” on page 186
094H Section 2.14.47, “VPD Data Register - VPDDR” on page 186
098H Section 2.14.48, “PM Capability Identifier Register - PM_Cap_ID” on page 187
099H Section 2.14.49, “PM Next Item Pointer Register - PM_Next_Item_Ptr” on page 187
09AH Section 2.14.50, “ATU Power Management Capabilities Register - APMCR” on page 188
09CH Section 2.14.51, “ATU Power Management Control/Status Register - APMCSR” on page 189
0A0H Section 4.7.20, “MSI Capability Identifier Register - Cap_ID” on page 429 a
0A1H Section 4.7.21, “MSI Next Item Pointer Register - MSI_Next_Ptr” on page 430
0A2H Section 4.7.22, “Message Control Register - Message_Control” on page 431
0A4H Section 4.7.23, “Message Address Register - Message_Address” on page 432
0A8H Section 4.7.24, “Message Upper Address Register - Message_Upper_Address” on page 433
0ACH Section 4.7.25, “Message Data Register- Message_Data” on page 434
0AEH Reserved
0B0H Section 4.7.26, “MSI-X Capability Identifier Register - MSI-X_Cap_ID” on page 435
0B1H Section 4.7.27, “MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr” on page 436
0B2H Section 4.7.28, “MSI-X Message Control Register - MSI-X_MCR” on page 437
0B4H Section 4.7.29, “MSI-X Table Offset Register — MSI-X_Table_Offset” on page 438
0B8H Section 4.7.30, “MSI-X Pending Bit Array Offset Register - MSI-X_PBA_Offset” on page 439
0BCH — 0C8H Reserved
0CCH Section 2.14.52, “ATU Scratch Pad Register - ATUSPR” on page 190
0D0H Section 2.14.53, “PCI-X Capability Identifier Register - PCI-X_Cap_ID” on page 190
0D1H Section 2.14.54, “PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr” on page 191
0D2H Section 2.14.55, “PCI-X Command Register - PCIXCMD” on page 191
0D4H Section 2.14.56, “PCI-X Status Register - PCIXSR” on page 193
0D8H Section 2.14.57, “ECC Control and Status Register - ECCCSR” on page 195
0DCH Section 2.14.58, “ECC First Address Register - ECCFAR” on page 198
0E0H Section 2.14.59, “ECC Second Address Register - ECCSAR” on page 199
0E4H Section 2.14.60, “ECC Attribute Register - ECCAR” on page 200
Table 26. Address Translation Unit Registers (Sheet 2 of 3)
Register
Offset
ATU Register Section, Name, Page