Intel CONTROLLERS 413808 - Manual (Page 446)

Intel
®
413808 and 413812—SRAM DMA Unit (SDMA)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
446 Order Number: 317805-001US
5.4 Register Definitions
The SDMA controller contains separate LocalToHost (L2H) and HostToLocal (H2L)
channels that are independent of each other. These are used simultaneously thus
allowing full duplex transfer to occur.
The location of these registers are specified as a relative offset to a 512KB aligned
global PMMR offset. The default for the 512KB aligned offset is 0 FFD8 0000H defined
by the PMMRBAR register.
Table 298. SDMA Controller Unit Registers
Section, Register Name, Acronym, Page
Section 5.4.1, “LocalToHost Destination Lower Address Register - L2H_DLAR” on page 447
Section 5.4.2, “LocalToHost Destination Upper Address Register - L2H_DUAR” on page 447
Section 5.4.3, “LocalToHost Source Lower Address Register - L2H_SLAR” on page 448
Section 5.4.4, “LocalToHost Byte Count Register - L2H_BCR” on page 449
Section 5.4.5, “LocalToHost Interrupt Counter/Acknowledge Register L2H_ICAR” on page 450
Section 5.4.6, “LocalToHost Control/Status Register - L2H_CSR” on page 451
Section 5.4.7, “LocalToHost Byte Swap Control Register - L2H_BSCR” on page 452
Section 5.4.8, “HostToLocal Destination Lower Address Register - H2L_DLAR” on page 452
Section 5.4.9, “HostToLocal Source Upper Address Register - H2L_SUAR” on page 453
Section 5.4.10, “HostToLocal Source Lower Address Register - H2L_SLAR” on page 453
Section 5.4.11, “HostToLocal Byte Count Register - H2L_BCR” on page 454
Section 5.4.12, “HostToLocal Interrupt Counter/Acknowledge Register - H2L_ICAR” on page 455
Section 5.4.13, “HostToLocal Control/Status Register - H2L_CSR” on page 456
Section 5.4.14, “HostToLocal Byte Swap Control Register - H2L_BSCR” on page 457