Intel CONTROLLERS 413808 - Manual (Page 473)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 473
SGPIO Unit—Intel
®
413808 and 413812
supports only SAS ports has the multiplexers selecting S_ACT[x] and S_STAT[x]
signals.
Note: The Protocol Engine activity and status signal pairs are not connected to the
corresponding SGPIO unit drive numbers.
Table 319. SGPIO Unit 1 Pin Multiplexing
Activity Pin Shared Pin Status Pin Shared Pin
S_ACT[4] SCLOCK[1] S_STAT[4] SLOAD[1]
S_ACT[5] TXRATE4[0] S_STAT[5] TXRATE4[1]
S_ACT[6] SDATAIN[1] S_STAT[6] SDATAOUT[1]
S_ACT[7] TXRATE6[0] S_STAT[7] TXRATE6[1]
Figure 54. 4138xx SGPIO Unit 1 Pin Mapping
S_ACT[6] / SDATAIN[1]
S_STAT[6] / SDATAOUT[1]
S_ACT[7] / TXRATE6[0]
S_STAT[7] / TXRATE6[1]
S_ACT[4] / SCLOCK[1]
S_STAT[4] / SLOAD[1]
S_ACT[5] / TXRATE4[0]
S_STAT[5] / TXRATE4[1]
TXRATE6[0]
TXRATE6[1]
TXRATE4[0]
TXRATE4[1]
SDATAOUT
SDATAIN
SLOAD
SCLOCK
STAT[3]
STAT[2]
STAT[1]
STAT[0]
ACT[3]
ACT[0]
ACT[1]
ACT[2]
Control bit 0 of the
SGICCR1 Register
S_STAT[5]
ACT[3]
SDATAIN
SDATAOUT
STAT[0]
SLOAD
ACT[2]
SCLOCK
ACT[0]
STAT[1]
ACT[1]
STAT[2]
STAT[3]
S_ACT[5]
S_STAT[7]
S_ACT[7]
S_STAT[1]
S_ACT[1]
S_STAT[3]
S_ACT[3]
S_STAT[0]
S_ACT[0]
S_STAT[2]
S_ACT[2]
S_STAT[4]
S_ACT[4]
S_STAT[6]
S_ACT[6]
SGPIO Unit 1
Dr0_ACT_in
Dr0_STAT_in
Dr1_ACT_in
Dr1_STAT_in
Dr2_ACT_in
Dr2_STAT_in
Dr3_ACT_in
Dr3_STAT_in
Dr4_ACT_in
Dr4_STAT_in
Dr5_ACT_in
Dr5_STAT_in
Dr6_ACT_in
Dr6_STAT_in
Dr7_ACT_in
Dr7_STAT_in
Dr2_STAT_out
Dr1_ACT_out
Dr0_STAT_out
Dr0_ACT_out
Dr3_ACT_out
Dr2_ACT_out
Dr1_STAT_out
Dr3_STAT_out