Intel CONTROLLERS 413808 - Manual (Page 156)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
156 Order Number: 317805-001US
2.14.14 Inbound ATU Upper Base Address Register 0 - IAUBAR0
This register contains the upper base address when decoding PCI addresses beyond 4
GBytes. Together with the Translation Base Address this register defines the actual
location the translation function is to respond to when addressed from the PCI bus for
addresses > 4GBytes (for DACs).
The programmed value within the base address register must comply with the PCI
programming requirements for address alignment. Refer to the PCI Local Bus
Specification, Revision 2.3 for additional information on programming base address
registers.
Note: When the Type Indicator of IABAR0 is set to indicate 32 bit addressability, the IAUBAR0
register attributes are read-only. Prior to changing the Type Indicator in the IABAR0 to
support 32-bit addressability, the IAUBAR0 must be written with zero unless it already
contains zero. Zero is the default value for the IAUBAR0.
Table 40. Inbound ATU Upper Base Address Register 0 - IAUBAR0
Bit Default Description
31:0 00000H
Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the
actual location the translation function is to respond to when addressed from the PCI bus for addresses
> 4GBytes.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+014H