Intel CONTROLLERS 413808 - Manual (Page 484)

Intel
®
413808 and 413812—SGPIO Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
484 Order Number: 317805-001US
6.6.8 SGPIO Output Data Select Register[0:7] x — SGODSR[0:7]x
The SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x provides the bit fields
to select the output signals. Each drive can support up to three output signals.
Table 328. SGPIO Output Data Select Register[0:7] x - SGODSR[0:7]x
Bit Default Description
31:12 00000H Reserved.
11 0
2
OD2 JOG Enable - When set this bit enables the jog mechanism to be applied on the input selected by
bits[09:08]. When cleared, the selected input is not altered.
10 0
2
Invert OD2 Selected Input - When set this bit causes the input selected by bits[09:08] to be inverted.
When cleared, the selected input is not altered.
09:08 00
2
OD2 Input Select - This field selects the input that drives output OD2 of Drive N, where N = 0 - 7.
Bits Selection
00
2
Fixed - High
01
2
Programmable pattern A
10
2
Programmable pattern B
11
2
Reserved
07 0
2
OD1 JOG Enable - When set this bit enables the jog mechanism to be applied on the input selected by
bits[05:04]. When cleared, the selected input is not altered.
06 0
2
Invert OD1 Selected Input - When set this bit causes the input selected by bits[05:04] to be inverted.
When cleared, the selected input is not altered.
05:04 00
2
OD1 Input Select - This field selects the input that drives output OD1 of Drive N, where N = 0 - 7.
Bits Selection
00
2
Fixed - High
01
2
Programmable pattern A
10
2
Programmable pattern B
11
2
Protocol Engine Status
03 0
2
OD0 JOG Enable - When set this bit enables the jog mechanism to be applied on the input selected by
bits[01:00]. When cleared, the selected input is not altered.
02 0
2
Invert OD0 Selected Input - When set this bit causes the input selected by bits[01:00] to be inverted.
When cleared, the selected input is not altered.
01:00 00
2
OD0 Input Select - This field selects the input that drives output OD0 of Drive N, where N = 0 - 7.
Bits Selection
00
2
Fixed - High
01
2
Programmable pattern A
10
2
Programmable pattern B
11
2
Protocol Engine Activity
Coprocessor
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Drive #
0
1
2
3
4
5
6
7
+2620H
+2624H
+2628H
+262CH
+2630H
+2634H
+2638H
+263CH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
SGPIO 0 Intel XScale ®
processor internal
bus address offset
Drive #
0
1
2
3
4
5
6
7
+26A0H
+26A4H
+26A8H
+26ACH
+26B0H
+26B4H
+26B8H
+26BCH
SGPIO 1
Intel XScale ®
processor internal
bus address offset