Intel CONTROLLERS 413808 - Manual (Page 501)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 501
System Controller (SC) and Internal Bus Bridge—Intel
®
413808 and 413812
7.5.2 South Internal Bus Address Test Control Register — SIBATCR
The SIBATCR can be used to inject an address parity error on the south internal
address bus. The user must provide the ID of the initiator and also set the enable bit.
The enable bit (when set) is used by hardware to inject an address parity error on the
next address transaction provided the programmed ID matches. The parity error is
injected in the address phase of the request. The enable bit is cleared by hardware in
the cycle that follows the address phase. This is done to prevent recurring parity errors.
Note: In order to inject the address parity error in the desired transaction, the user must try
to write this register immediately before the transaction is issued on the internal bus.
Table 335. South Internal Bus Address Test Control Register — SIBATCR
Bit Default Description
31:21 000H Reserved.
20:16 00000
2
Address Parity Mask bits — Each bit of the generated address parity is XORed with the appropriate bits
in this mask field before the parity bits are driven on the north internal bus. Bit16 corresponds to
address parity bit 0, bit 17 corresponds to address parity bit 1, and so on.
07:04 0000
2
Initiator ID — This field specifies the initiator ID of the address (for example, the unit sourcing the
address). Refer to Table 331, “Data Parity Testing Completer IDs” on page 489 for the initiator IDs.
03:01 000
2
Reserved.
00 0
2
Enable bit — When this bit is set, an address parity error is injected on the next address request made
when the initiator ID of the transaction matches the specified Initiator ID in bits[07:04]. This bit is set
by software and cleared by hardware.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rv
na
rv
na
rv
na
rw
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
South XBG
internal bus address offset
+1644H