Intel CONTROLLERS 413808 - Manual (Page 3)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 3
Contents—Intel
®
413808 and 413812
Contents
1.0 Introduction...............................................................................................................36
1.1 Design-in Considerations....................................................................................38
1.1.1 Software ...............................................................................................39
1.2 Documentation References ................................................................................. 40
1.3 About This Document......................................................................................... 41
1.3.1 How To Read This Document ................................................................... 41
1.3.2 Other Relevant Documents ...................................................................... 41
1.4 About the Intel
®
413808 and 413812 I/O Controllers in TPER Mode ......................... 42
1.5 Intel
®
413808 and 413812 I/O Controllers in TPER Mode Features...........................44
1.5.1 Host Interface........................................................................................ 44
1.5.2 Intel XScale
®
Processor .......................................................................... 44
1.5.3 Internal Busses...................................................................................... 45
1.5.4 Application DMA Controller ...................................................................... 45
1.5.5 Address Translation Unit .........................................................................45
1.5.6 Messaging Unit ...................................................................................... 46
1.5.7 DDR Memory Controller........................................................................... 46
1.5.8 Peripheral Bus Interface.......................................................................... 46
1.5.9 Performance Monitoring Unit....................................................................46
1.5.10 I
2
C Bus Interface Unit............................................................................. 46
1.5.11 UART Unit ............................................................................................. 46
1.5.12 Interrupt Controller Unit.......................................................................... 46
1.5.13 Internal Bus System Controller.................................................................47
1.5.14 Inter-Processor Communication................................................................ 47
1.5.15 Inter-Processor Messaging Unit ................................................................ 47
1.5.16 Timers.................................................................................................. 47
1.5.17 GPIO .................................................................................................... 47
1.5.18 FSENG.................................................................................................. 47
1.6 Terminology and Conventions ............................................................................. 48
1.6.1 Representing Numbers............................................................................48
1.6.2 Fields ................................................................................................... 48
1.6.3 Specifying Bit and Signal Values............................................................... 49
1.6.4 Signal Name Conventions........................................................................ 49
1.6.5 Terminology .......................................................................................... 49
2.0 Address Translation Unit (PCI-X) .................................................................................. 50
2.1 Overview ......................................................................................................... 50
2.2 ATU Address Translation ....................................................................................53
2.2.1 Inbound Transactions ............................................................................. 55
2.2.1.1 Inbound Address Translation ......................................................56
2.2.1.2 Inbound Write Transaction .........................................................59
2.2.1.3 Inbound Read Transaction.......................................................... 61
2.2.1.4 Inbound Configuration Cycle Translation ......................................64
2.2.1.5 Discard Timers .........................................................................66
2.2.2 Outbound Transactions- Single Address Cycle (SAC) Internal Bus Transactions...
67
2.2.2.1 Outbound Address Translation - Internal Bus Transactions.............. 68
2.2.2.2 Outbound Address Translation Windows....................................... 69
2.2.3 Outbound Write Transaction ....................................................................72
2.2.4 Outbound Read Transaction..................................................................... 74
2.2.5 Outbound Configuration Cycle Translation.................................................. 75
2.2.5.1 PCI-X Mode 1 Considerations for Outbound Configuration Cycles ..... 75
2.2.5.2 PCI-X Mode 2 Considerations for Outbound Configuration Cycles ..... 76
2.2.5.3 Outbound Configuration Cycle Error Conditions ............................. 76