Intel CONTROLLERS 413808 User Manual

Page 103

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Intel

®

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

103

Address Translation Unit (PCI-X)—Intel

®

413808 and 413812

2.7.3.8

Outbound Split Write Uncorrectable Data Error Message

The ATU claims a Split Completion Error Message that indicates an uncorrectable data

error has occurred on one of the ATUs non-posted (I/O or Configuration) write requests

(Message Class = 2h, Message Index = 01h -- Uncorrectable Split Write Data Error or

Message Class = 1h, Message Index = 02h --Uncorrectable Write Data Error).
When the ATU receives a Split Completion Error Message indicating an uncorrectable

data error for an outstanding Configuration or I/O (split) write request, the error is

recorded, and

SERR#

is asserted (when enabled). Specifically, the following actions

with the given constraints are taken by the ATU:

• When the Parity Error Response bit in the ATUCMD is set, these actions are taken:

— The Master Parity Error bit in the ATUSR is set.

— When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear,

set the PCI Master Parity Error bit in the ATUISR. When set, no action.

— When the

SERR#

Enable bit in the ATUCMD is set, and the Uncorrectable Data

Error Recover Enable bit in the PCIXCMD register is clear, assert

SERR#

,

otherwise no action. When the ATU asserts

SERR#,

additional actions are

taken:

Set the

SERR#

Asserted bit in the ATUSR.

When the ATU

SERR#

Asserted Interrupt Mask Bit in the ATUIMR is clear, set

the

SERR#

Asserted bit in the ATUISR. When set, no action.

When the ATU

SERR#

Detected Interrupt Enable Bit in the ATUCR is set, set

the

SERR#

Detected bit in the ATUISR. When clear, no action.

• The Received Split Completion Error Message bit in the PCIXSR is set (based on bit

30 of the completer attributes being set). When the ATU sets this bit, additional

actions are taken:

— When the ATU Received Split Completion Error Message Interrupt Mask bit in

the ATUIMR is clear, set the Received Split Completion Error Message bit in the

ATUISR. When set, no action.

• The transaction associated with the Split Completion Error Message is discarded.

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