Intel CONTROLLERS 413808 - Manual (Page 820)

Intel ® 413808 and 413812—Peripheral Registers
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
820 Order Number: 317805-001US
Table 549. Coprocessor Register Locations (Sheet 1 of 4)
Peripheral Register Description (Name) Coprocessor Field CR
m
Coprocessor
Register
(Field CR
n
)
In
ter
-Pr
oc
es
so
r
Co
mm
un
ica
tio
n
Core Identification Register — CIDR CP6
0
Register 0
Reset Cause Status Register — RCSR
1
Register 0
Software Interrupt Generation Register —
SINTGENR
Register 1
Targeted Reset Register — TARRSTR Register 2
Undefined
Register 3
through
Register 7
Inbound MSI Interrupt Pending Register 0 Register 8
Inbound MSI Interrupt Pending Register 1 Register 9
Inbound MSI Interrupt Pending Register 2 Register 10
Inbound MSI Interrupt Pending Register 3 Register 11
Undefined
Register 12
through
Register 15
In
ter
ru
pt
Co
ntr
ol
Un
it
Interrupt Base Register CP6
2
Register 0
Undefined Register 1
Interrupt Size Register Register 2
IRQ Interrupt Vector Register Register 3
FIQ Interrupt Vector Register Register 4
Undefined Register 4–7
Inter-Processor Interrupt Pending Register Register 8
Undefined Register 9–15
Interrupt Pending Register 0 3 Register 0
Interrupt Pending Register 1 Register 1
Interrupt Pending Register 2 Register 2
Interrupt Pending Register 3 Register 3
Undefined Register 4–15
Interrupt Control Register 0
4
Register 0
Interrupt Control Register 1 Register 1
Interrupt Control Register 2 Register 2
Interrupt Control Register 3 Register 3
Undefined Register 4–15