37 expansion rom limit register - erlr, Table 64. expansion rom limit register - erlr, 37expansion rom limit register - erlr – Intel CONTROLLERS 413808 User Manual
Page 175: 64 expansion rom limit register - erlr, Section 2.14.37, Address translation unit (pci-x)—intel, Bit default description, Intel
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
175
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.37 Expansion ROM Limit Register - ERLR
The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU
defines as Expansion ROM address space. Block size is programmed by writing a value
into the ERLR.
Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12,
with a one to one correspondence. A value of 0 in a bit within the ERLR makes the
corresponding bit within the ERBAR a read only bit which always returns 0. A value of 1
in a bit within the ERLR makes the corresponding bit within the ERBAR read/write from
PCI.
Table 64. Expansion ROM Limit Register - ERLR
Bit
Default
Description
31:12
000000H Expansion ROM Limit - Memory block size required for Expansion ROM translation unit. Default value 0,
indicates no Expansion ROM address space and all bits within ERBAR are read only with a value of 0.
11:00
000H
Reserved
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+064H