Intel CONTROLLERS 413808 - Manual (Page 662)

Intel ® 413808 and 413812—UARTs
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
662 Order Number: 317805-001US
13.3 Theory of Operation
The format of a UART data frame is shown in Figure 89 .
Each data frame is between 7 bits and 12 bits long, depending on the size of data
programmed and when parity and stop bits are enabled. The frame begins with a start
bit that is represented by a high-to-low transition. Next, five to eight bits of data are
transmitted, beginning with the least significant bit. An optional parity bit follows,
which is set when even parity is enabled and an odd number of ones exist within the
data byte; or when odd parity is enabled and the data byte contains an even number of
ones. The data frame ends with one, one-and-one-half or two stop bits (as
programmed by the user), which is represented by one or two successive bit periods of
a logic one.
NRZ coding can be used by the UART to represent individual bit values. NRZ coding is
enabled when Interrupt Enable Register (IER) bit-5 is set to high. A one is represented
by a line transition and a zero is represented by no line transition. Figure 90 shows the
NRZ coding of the data byte 8b 0100 1011. Note that the byte’s LSB is transmitted
first.
The unit is disabled upon reset, and users need to enable the unit by setting the UART
Unit Enable bit (UUE, bit-6) of Interrupt Enable Register. When the unit is enabled, the
receiver starts looking for the start bit of a frame; the transmitter sends data to the
transmit data pin when there is data available in the transmit FIFO. Transmit data can
be written to the FIFO before the unit is enabled. When the UART is disabled, the
transmitter/receiver finishes the current byte being transmitted/received (when it is in
the middle of transmitting/receiving a byte), and stops transmitting/receiving more
data. Disabling the UART with the UUE bit does not clear transmission/reception with
the original data.
Each UART has a Transmit FIFO and a Receive FIFO each holding 64 characters of data.
There are two methods for moving data into/out of the FIFOs: Interrupts and
Polling .
Figure 89. Example UART Data Frame
Start
Bit
Data<
0>
Data<
1>
Data<
2>
Data<
3>
Data<
4>
Data<
5>
Data<
6>
Data<
7>
Parity
Bit
Stop
Bit 1
Stop
Bit 2
TXD or RXD pin
LSB MSB
Shaded bits are optional and can be programmed by user. —>
Figure 90. NRZ Bit Encoding Example – (0100 1011)
Digital
Data
NRZ
Data
Bit
Value
1 1 0 1 0 0 1 0
LSB MSB
B6281-01