Intel CONTROLLERS 413808 - Manual (Page 426)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
426 Order Number: 317805-001US
4.7.16 MU MSI-X Table Message Upper Address Registers -
M_MT_MUAR[0:7]
The MU MSI-X Table Message Upper Address Register contains the upper 32 bits of the
MSI-X message address. An entry in the MSI-X Table is made up of four DWORDs.
Note: The M_MT_MUAR[0:7] registers are not reset with an internal bus reset.
Table 281. MU MSI-X Table Message Upper Address Registers - M_MT_MUAR [0:7]
Bit Default Description
31:00 0000 0000H Message Upper Address: This field contains the upper 32 bits of the MSI-X Message Address.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible M_MT_MAR0
M_MT_MAR1
M_MT_MAR2
M_MT_MAR3
M_MT_MAR4
M_MT_MAR5
M_MT_MAR6
M_MT_MAR7
internal bus address
offset
5004H
5014H
5024H
5034H
5044H
5054H
5064H
5074H
M_MT_MAR0
M_MT_MAR1
M_MT_MAR2
M_MT_MAR3
M_MT_MAR4
M_MT_MAR5
M_MT_MAR6
M_MT_MAR7
MU/PCI Base Address
Offset
1004H
1014H
1024H
1034H
1044H
1054H
1064H
1074H