Intel CONTROLLERS 413808 - Manual (Page 242)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
242 Order Number: 317805-001US
3.3.1.4 Inbound I/O Cycle Translation
Inbound address window 2 can be configured to accept I/O Read and I/O Write
transactions by setting the Memory/IO space indicator bit to 1 in the “Inbound ATU
Base Address Register 2 - IABAR2” on page 310 . All I/O cycles are 32-bit transactions
(DWORD).
For inbound I/O reads, the INPQ is used in the same manner as inbound memory read
operations and the exception cases are identical. However, the internal bus cycle that
results is always be a 32-bit transaction.
For inbound I/O writes, the ATU uses the INPHQ to hold both the header and the INPDQ
to hold the data. An I/O write TLP with poisoned data results in the data being dropped
and a Completion with Completions status of UR is returned to the requester.
When there are no errors during the request cycle, transaction ordering and priority are
satisfied. Next, the internal bus master interface requests the internal bus and deliver
the write data to the target as defined in Section 3.3.1.2 .
The status of the transaction on the internal bus is returned to the requestor on the PCI
Express Link. When the Write Cycle Master Aborts on the Internal Bus, a Completion
with status of Completer Abort is returned.
3.3.1.5 Inbound Configuration Cycle Translation (ID Routed)
The 4138xx ATU only accepts Type 0 configuration requests with a function number of
zero when bit 7 of the ATUHTR (see Section 3.17.11, “ATU Header Type Register -
ATUHTR” on page 302 ) is cleared or function numbers of zero and one when bit 7 of the
ATUHTR is set.
The ATU is a native PCI Express device that supports both the standard PCI express
capability structure and the PCI Express Extended capability structure. The ATU
configuration space is selected by any PCI Express Type 0 configuration cycle targeting
function 0. The bus number and device number is captured from all valid Type 0
configuration write TLPs that target an enabled function.
For inbound configuration reads, the INPQ is used in the same manner as inbound
memory read operations.
For inbound configuration writes, the ATU uses the INPQ to hold both the header and
the data. An configuration write TLP with poisoned data results in the data being
dropped and an Completion with Completions status of UR is returned to the requester.
When there are no errors during the request cycle, transaction ordering and priority are
satisfied. Next, the internal bus master interface requests the internal bus and deliver
the write data to the target as defined in Section 3.3.1.2 .
Since Master Aborts and Target Aborts cannot occur during configuration cycles on the
internal bus, a Completion TLP with Successful Completion (SC) status is generated for
all configuration cycles.
When the Configuration Request Retry bit is set (PCSR[2)], the Configuration Request
cycle is terminated with a Configuration Request Retry Status (CRS).