7 outbound interrupt status register - oisr, 272 outbound interrupt status register - oisr, Messaging unit—intel – Intel CONTROLLERS 413808 User Manual
Page 417: Bit default description
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
417
Messaging Unit—Intel
®
413808 and 413812
4.7.7
Outbound Interrupt Status Register - OISR
The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It
records the status of Host I/O Interface interrupts generated by the Message Registers,
Doorbell Registers, and the Circular Queues. The generation of Host I/O Interface
interrupts recorded in the Outbound Interrupt Status Register may be masked by
setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the bits
in this register are Read Only. For those bits, the interrupt must be cleared through
another register.
Table 272. Outbound Interrupt Status Register - OISR
Bit
Default
Description
31
0
2
Firmware Interrupt Pending - This bit is set when the Firmware Interrupt bit is set in the Outbound Reset
Control and Status Register. To clear this bit (and the interrupt), the Firmware Interrupt bit must be
cleared in the Outbound Reset Control and Status Register.
30:08
000000H
000
2
Reserved
07
0
2
PCI Interrupt D - This bit is set when the PCI Interrupt D bit is set in the Outbound Doorbell Register. To
clear this bit (and the interrupt), the PCI Interrupt D bit must be cleared.
06
0
2
PCI Interrupt C - This bit is set when the PCI Interrupt C bit is set in the Outbound Doorbell Register. To
clear this bit (and the interrupt), the PCI Interrupt C bit must be cleared.
05
0
2
PCI Interrupt B - This bit is set when the PCI Interrupt B bit is set in the Outbound Doorbell Register. To
clear this bit (and the interrupt), the PCI Interrupt B bit must be cleared.
04
0
2
PCI Interrupt A - This bit is set when the PCI Interrupt A bit is set in the Outbound Doorbell Register. To
clear this bit (and the interrupt), the PCI Interrupt A bit must be cleared.
03
0
2
Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is
cleared when any prefetch data has been read from the Outbound Queue Port.
02
0
2
Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound
Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound
Doorbell Register must all be clear.
01
0
2
Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is
written. Clearing this bit clears the interrupt.
00
0
2
Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is
written. Clearing this bit clears the interrupt.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
ro
ro
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rc
rc
rc
rc
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
MU/PCI Base Address Offset
OISR: 0030H
internal bus address offset
OISR: 4030H