Intel CONTROLLERS 413808 - Manual (Page 141)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 141
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
Following the Capability Identifier Register is the single byte Next Item Pointer Register
( Section 4.7.27, “MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr” ) which
indicates the configuration offset of an additional Extended Capabilities Header, when
supported. In the ATU, the Next Item Pointer Register is set to A0H indicating that
there is an additional Extended Capabilities Headers supported in the ATUs
configuration space.
Note: MSI-X Capability Registers are defined in Chapter 4.0, “Messaging Unit.”
The first byte at the Extended Configuration Offset A0H is in Section 4.7.20, “MSI
Capability Identifier Register - Cap_ID” . This identifies this Extended Configuration
Header space as the type defined by the PCI Local Bus Specification, Revision 2.3.
Following the Capability Identifier Register is the single byte
Section 4.7.21, “MSI Next
Item Pointer Register - MSI_Next_Ptr” , which indicates the configuration offset of an
additional Extended Capabilities Header, when supported. In the ATU, the Next Item
Pointer Register is set to D0H indicating that there is an additional Extended
Capabilities Headers supported in the ATUs configuration space.
The first byte at the Extended Configuration Offset D0H is the PCI-X Capability
Identifier Register ( Section 2.14.53 ). This identifies this Extended Configuration Header
space as the type defined by the PCI-X Protocol Addendum to the PCI Local Bus
Specification, Revision 2.0. Indicated by bits 13:12 of the PCI-X Command Register, the
4138xx includes version 1 of the PCI-X Capabilities List Item indicating the 24 byte
length of the item and the fact that ECC protection is provided in Mode 2 only.
Following the Capability Identifier Register is the single byte Next Item Pointer Register
( Section 2.14.54 ) which indicates configuration offset of an additional Extended
Capabilities Header, when supported. In the ATU, the Next Item Pointer Register is set
to E8H indicating that there is an additional Extended Capabilities Headers supported in
the ATUs configuration space.
Figure 18. ATU Interface Extended Configuration Header Format (MSI Capability)
A0H
A4H
MSI Capability ID MSI Next Item Pointer MSI Message Control
MSI Message Address
MSI Message Upper Address A8H
ACH MSI Message Data Reserved
B6328-01
Figure 19. ATU Interface Extended Configuration Header Format (PCI-X Capability
Type 1)
D0H
D4H
PCI-X Capability ID Next Item Pointer PCI-X Command
PCI-X Status
D8H
DCH
E0H
E4H
ECC Control and Status (Mode 2)
ECC First Address (Mode 2)
ECC Second Address (Mode 2)
ECC Attribute (Mode 2)
B6329-01