Address translation unit (pci-x)—intel, Bit default description, Intel – Intel CONTROLLERS 413808 User Manual
Page 217
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
217
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.78 Outbound Upper 32-bit Memory Window Translate Value
Register 3 - OUMWTVR3
The Outbound Upper 32-bit Memory Window Translate Value Register 3 (OUMWTVR3)
defines the upper 32-bits of address used during a dual address cycle. This enables the
outbound ATU to directly address anywhere within the 64-bit host address space. When
this register is all-zero, then a SAC is generated on the PCI bus.
Table 105. Outbound Upper 32-bit Memory Window Translate Value Register 3-
OUMWTVR3
Bit
Default
Description
31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC).
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+324H