Intel CONTROLLERS 413808 - Manual (Page 113)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 113
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.7 Corrupted or Unexpected Split Completions
Warning:
When any of the errors discussed in this section actually occur, a catastrophic system
failure is likely to result from which the PCI-X Protocol Addendum to the PCI Local Bus
Specification, Revision 2.0 provides no recovery mechanism. In these cases, the ATU
may be communicating with a non-compliant target device or the system may not be
configured properly.
2.7.7.1 Completer Address
The ATU only asserts DEVSEL# for split completion transactions where the Sequence
ID (Requester ID & Tag) matches that of a currently outstanding split request in the
OTQ.
Conversely, the ATU does not assert
DEVSEL# for any split completion transaction
where either the Requester ID does not match that of the ATU or the Tag does not
match that of any currently outstanding split request. No further action is taken.
When the Sequence ID of a split completion transaction matches that of an outstanding
request, but the Lower Address field is not valid, the ATU accepts the split completion
transaction in its’ entirety according to the invalid Lower Address field and set the
Unexpected Split Completion bit in the PCIXSR. No further action is taken.
2.7.7.2 Completer Attributes
When the Sequence ID of a split completion transaction matches that of an outstanding
request, but the Byte Count is not valid, the ATU accepts the split completion
transaction in its’ entirety according to the invalid byte count field and set the
Unexpected Split Completion bit in the PCIXSR. In this case, the ATU discards all the
data. No further action is taken.