Intel CONTROLLERS 413808 - Manual (Page 803)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 803
Peripheral Registers—Intel ® 413808 and 413812
19.6.1.4 I/O Pad Control
The I/O Pad Control is allocated 512 Bytes of PMMR registers space and is always
located at offset +2000H relative to the PMMRBAR.
Use the following equation to calculate the actual register address:
Internal Bus Address = PMMRBAR + I/O Pad Control Base Address Offset + Register
Offset.
Note: The PBI drive strength register is described in the Peripheral Bus Interface chapter.
Table 530. I/O Pad Control Base Address Offset.
Unit Associated Unit Interface
I/O Pad Control Base Address Offset
(Relative to PMMRBAR)
I/O Pad Control
Reserved +2000H
Peripheral Bus Interface +2080H
PCI Interface +2100H
Other Units +2180H
Table 531. I/O Pad Control Unit
Unit Register Description (Name)
Register
Size in
Bits
Internal Bus
Address Offset
(Relative to I/O Pad
Control Base
Address Offset)
Peripheral Bus
Interface
PBI Drive Strength Control Register — PBDSCR 32 +00H
Reserved x +04H through +7FH
PCI Interface
PCIX RCOMP Control Register — PRCR 32 +00H
PCIX Pad ODT Drive Strength Manual Override
Values Registers — PPODSMOVR
32 +04H
PCIX PAD DRIVE STRENGTH manual override
values register (3.3V/1.5V switch
supply voltage) — PPDSMOVR3.3_1.5
32 +08H
PCIX PAD DRIVE STRENGTH manual override
values register(3.3V dedicated
supply voltage) — PPDSMOVR3.3
32 +0CH
Reserved x +10H through +7FH
Other Units 1
Reserved 32 +00H
Reserved 32 +04H
Reserved 32 +08H
Reserved 32 +0CH
Reserved 32 +10H
Unique ID Register 0 — UID0 32 +14H
Unique ID Register 1 — UID1 32 +18H
Reserved x +1CH through +7FH
Notes:
1. Registers that belong in this group are documented in the Peripheral Bus Interface Unit chapter.