Address translation unit (pci-x)—intel, Bit default description, Intel – Intel CONTROLLERS 413808 User Manual
Page 205
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
205
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.65 Inbound ATU Upper Base Address Register 3 - IAUBAR3
This register contains the upper base address when decoding PCI addresses beyond 4
GBytes. Together with the Translation Base Address this register defines the actual
location the translation function is to respond to when addressed from the PCI bus for
addresses > 4GBytes (for DACs).
The programmed value within the base address register must comply with the PCI
programming requirements for address alignment. Refer to the PCI Local Bus
Specification, Revision 2.3 for additional information on programming base address
registers.
Note:
When the Type indicator of IABAR3 is set to indicate 32 bit addressability, the IAUBAR3
register attributes are read-only. By default the IAUBAR3 register has read-only
attributes. Prior to changing the Type Indicator in the IABAR3 to support 32-bit
addressability, the IAUBAR3 must be written with zero unless it already contains zero.
Zero is the default value for IAUBAR3.
Table 92. Inbound ATU Upper Base Address Register 3 - IAUBAR3
Bit
Default
Description
31:0
00000H
Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define the
actual location the translation function is to respond to when addressed from the PCI bus for addresses
> 4GBytes.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+204H