Intel, Bit default description, Processor local bus address – Intel CONTROLLERS 413808 User Manual
Page 506: 1784h south xbg
Intel
®
413808 and 413812—System Controller (SC) and Internal Bus Bridge
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
506
Order Number: 317805-001US
7.5.7
Bridge Window Upper Base Address Register — BWUBAR
The Bridge Window Upper Base Address Register (BWUBAR) provides the upper 4 bits
of the block of memory addresses where the Bridge Memory Window begins. The
BWUBAR is used in conjunction with the BWBAR to form a 36-bit base address register.
Refer to the
Section 7.5.6, “Bridge Window Base Address Register — BWBAR” on
Table 340. Bridge Window Upper Base Address Register — BWUBAR
Bit
Default
Description
31:04
0000 000H Reserved.
03:00
0H
Bridge Upper Memory Window Base Address:
These bits are the upper 4-bits of the 36-bit base
address that defines the actual location the Bridge responds to for accesses to the Bridge Memory
Window on the South Internal Bus.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale
®
processor Local Bus Address
Offset
+1784H
South XBG