Intel CONTROLLERS 413808 - Manual (Page 197)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 197
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2 0
2
Additional Correctable ECC Error - This bit is set when the 4138xx detects a correctable ECC error while
error correction is enabled and the device is already indicating some other ECC error (i.e. the ECC Error
Phase register is non-zero).
0 = No additional correctable ECC error has been detected.
1 = One or more additional correctable ECC errors have been detected.
1:0 00
2
Reserved
Table 84. ECC Control and Status Register - ECCCSR (Sheet 3 of 3)
Bit Default Description
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro
ro
rw
rw
rv
rv
wo
wo
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rv
rv
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
WO = Write Only
NA = Not Accessible
Internal Bus Address
+0D8H