Intel CONTROLLERS 413808 - Manual (Page 723)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 723
General Purpose I/O Unit—Intel ® 413808 and 413812
15.0 General Purpose I/O Unit
Note: For TPER mode the register interface defined here is used. For 4138xx non-TPER mode,
see the SAS/SATA Command Summary for API to control the GPIO units. Some
limitations apply when controlling via the API.
This chapter describes the Intel
®
413808 and 413812 I/O Controllers in TPER Mode
(4138xx) General Purpose I/O Unit; operation modes, setup, external memory
interface, and implementation of General Purpose I/Os (GPIOs).
15.1 General Purpose Input Output Support
Twelve pins are provided as General Purpose Input Output (GPIO) pins. The Twelve pins
are GPIO[15:0] . These pins can be used by the Intel XScale
®
processors to control or
monitor external devices in the I/O subsystem.
15.1.1 General Purpose Inputs
The current state of the twelve GPIO pins can be read in HPI# .
Note: When configured as GPIOs, the twelve GPIO pins can be used as (up to) 12 additional
external interrupt inputs dedicated to the Intel XScale
®
processor. This feature is
available on a per pin basis simply by programming the INTCTL[3:0] registers.
15.1.2 General Purpose Outputs
The output function of the GPIO pins is controlled by two registers, as stated in Section
15.2.3, “GPIO Output Data Register — GPOD” on page 728 ) and Section 15.2.1, “GPIO
Output Enable Register — GPOE” on page 725 ).
The output enables are mapped on a per bit basis to each of the data bits in the GPIO
Output Data Register. When a bit of the GPIO Output Enable Register is cleared, the
corresponding data bit value in the GPIO Output Data Register is actively driven on the
appropriate GPIO pin.
15.1.3 Reset Initialization of General Purpose I/O Function
• GPIO Input Data Register is initialized to the state of GPIO[15:0] bus upon
assertion of P_RST# . Note that GPIO[3:0] pins are multiplexed with the PCI-X
interrupts P_INT[D:A]# and, therefore, are initialized as output pins when the
PCI-X interface is used as an endpoint.
• GPIO Output Data Register is initialized to all zeros upon assertion of P_RST# .
• GPIO Output Enable Register is initialized to FFFFH upon assertion of P_RST# . This
means that GPIO[15:0] are initialize as inputs.
• GPIO[15:0] pins are tristated during P_RST# assertion.