Intel CONTROLLERS 413808 - Manual (Page 275)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 275
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.9.2 Parity Error on the Internal Bus
The 4138xx provides support for byte-wise parity protection on the internal bus. The
internal bus consists of a 36 bit address bus and 128 bit data bus; both are protected
by byte-wise parity. The internal bus parity protection is provided independent of the
operating mode of the ATU’s PCI interface.
When initiating transactions on the internal bus, the ATU’s internal bus interface
generates byte-wise parity. As a target the ATU checks byte-wise parity.
3.9.3 ATU Error Summary
Table 135, “PCI Express Error Summary” summarizes the ATU error reporting for PCI
Express Link errors, Table 136, “Root Complex Error Summary” summarizes the error
reporting when operating as a Root Complex, and Table 137, “Internal Bus Error
Summary” summarizes the ATU error reporting for internal bus errors. The tables
assume that all error reporting is enabled through the appropriate command registers
(unless otherwise noted).
Example: A poisoned TLP is received.
• Depending on the setting in the ERRUNC_SEV register, send
ERR_FATAL/NON_FATAL to the root complex.
• Log the error in the Advanced Error registers (ADVERR_CTL, ADVERR_LOG) as well
as the PCI Interface Error registers (PIE_CSR, PIE_LOG, PIE_DLOG)
• Set the Detected Parity Error, SERR# Asserted, and possible the Master Data Parity
Error bits in the ATUCR.
• Set the Fatal Error Detected or Non-Fatal Error Detected in the Device Status
register (PE_DSTS) depending on the error message sent
• Set the Poisoned TLP Received status bit in the ERRUNC_STS register
• Set the Poisoned TLP Received status bit in the PIE_STST register.
• Depending on the mask bits, set any or all of the following bits in the ATUISR
— PCI Interface Error Interrupt
— Uncorrectable Error Transmitted Interrupt
— Detected Parity Error Interrupt
— Master Data Parity Error Interrupt
• Possible mask bits are the SERR# Enable (ATUCMD[8]), Fatal/Non-Fatal Error
Reporting Enable (PE_DCTL[2 or 1]), Interrupt Masks (ATUIMR[8,4,0]) and logging
masks (ERRUNC_MSK[12] & PIE_MSK[12]).