Intel CONTROLLERS 413808 - Manual (Page 576)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
576 Order Number: 317805-001US
10.5.3 Intel
®
413808 and 413812 I/O Controllers in TPER Mode:
Internal Peripheral Interrupt
The 4138xx Interrupt Controller receives inputs from multiple internal interrupt
sources. All pending interrupts required during normal operation of the various
peripheral units are available in either the IINTSRC[3:0] or FINTSRC[3:0] registers
depending on the value in INTSTR[3:0]. To provide the best latency for high
performance event driven activities, the Application DMAs interrupts are fully
demultiplexed into the interrupt source registers for FIQ and IRQ so that software does
not need to access these peripheral units to diagnose the exact source and cause of the
interrupt. The IINTSRC[3:0] and the FINTSRC[3:0] registers also include pending
interrupts that indicate that an error has occurred in one of the peripheral units. For the
interrupts that indicate errors, more detail about the exact cause of the interrupt can
be determined by reading the status register of the respective peripheral unit.